1. Field of the Invention
The present invention relates to an active matrix display device having switching elements, such as thin film transistors (hereinafter referred to as "TFT"), and using liquid crystals as a display medium.
1.1 Related Prior Applications
This application is related to commonly assigned U.S. patent application Ser. No. 07/527,191 filed May 23, 1990 by Shimada, Tanaka, Saito and Ujimasa entitled "An Active-Matrix Display Device with Added Capacitance Electrode Wire and Secondary Wire Connected Thereto".
2. Description of the Prior Art
Recently, research on active matrix display devices using liquid crystals or the like as a display medium has been very actively pursued. More particularly, research efforts directed toward the development of liquid crystal displays (hereinafter referred to as "LCD") known as plane displays have been steadily obtaining good results. There are at present two currents of research aimed at development of active matrix type LCD. One is oriented toward the development of an extra large display screen intended for realization of a so-called "wall type television". The other is oriented toward the development of a high-precision display screen. Active matrix type LCD in particular, which are small in size and able to perform a high-precision display function, are very promising in that large demand could be expected for such an LCD for use as a video-camera color view finder.
An IC chip for driving a TFT array is mounted on an active matrix type LCD. In an active matrix type LCD which is of a small size and is designed to perform high-precision display, spacing between adjacent connection terminals is very limited and, therefore, mounting of the IC chip is difficult. With a view to overcoming this difficulty, in a small-sized, high-precision active matrix type LCD, a drive circuit is formed on a substrate having a TFT array formed thereon.
A basic arrangement of an active matrix display device in which a drive circuit and a TFT array are formed on a common substrate is schematically shown in FIG. 7. In this display device, a gate drive circuit 54, a source drive circuit 55, and a TFT array area 53 are formed on a substrate 50. In the TFT array area 53 there are arranged a multiplicity of parallel gate bus lines 51 extending from the gate drive circuit 54. A multiplicity of source bus lines 52 extending from the source drive circuit 55 are arranged in intersecting relation with the gate bus lines 51. Additional capacitor common lines 59 are arranged in parallel to the gate bus lines 51.
A TFT 56, a picture element 57, and an additional capacitor 58 are arranged in a rectangular area defined between each two adjacent source bus lines 52 and each two adjacent gate bus lines 51. A gate electrode of the TFT 56 is connected to one gate bus line 51, and a source electrode thereof is connected to one source bus line 52. A liquid crystal layer is contained between a pixel electrode connected to a drain electrode and a counter electrode on an opposite base to form the picture element 57. The additional capacitor 58 is formed between the TFT 56 and one additional capacitor common line 59. The additional capacitor common line 59 is connected to an electrode with the same potential as the opposed electrodes which constitute the picture element 57.
In this display device, TFTs 56 connected to a gate bus line 51 are turned on by a signal from the gate drive circuit 54. A video signal is sent from the source drive circuit 55 to picture elements 57 through source bus lines 52. Each video signal is retained between the pixel electrode and counter electrode which constitutes each picture element 57 after the relevant TFT 56 has been turned off. In small-size high-precision active matrix type LCD, the area of each picture element is very small and, accordingly, the capacity of a capacitor formed between each pixel electrode and corresponding counter electrode is small. This gives rise to a problem that a video signal cannot be retained for the required period of time. The potential fluctuation of the picture elements due to the potential fluctuation of the bus line is another possible problem. Therefore, in order to compensate for the capacitor deficiency of the capacitor between each pixel electrode and the corresponding counter electrode, additional capacitors 58 are provided in parallel to individual picture elements 57. One electrode of each additional capacitor 58 is connected to the drain electrode of the relevant TFT 56. The other electrode of the additional capacitor 58 must be of the same potential as the relevant counter electrode. Therefore, this electrode is connected to an electrode of the same potential as the counter electrode through the additional capacitor common line 59.
In many such active matrix display devices of the type having drive circuits integrally formed therein, polycrystalline silicon is used for TFT semiconductor layers. One reason is that polycrystalline silicon affords a high degree of electron and hole mobility. Another reason is that the material is useful for making n-type and p-type TFTs and can therefore be advantageously utilized in constructing CMOS.
An active matrix substrate used in the display device of FIG. 7 is shown, by way of example, in plan view in FIG. 4. Sections taken along line V--V and line VI--VI in FIG. 4 are shown respectively in FIGS. 5 and 6. A semiconductor layer 33, and a lower capacitor electrode 46 which one electrode of an additional capacitor 32 (FIG. 6) are integrally pattern-formed on a glass substrate 30. The semiconductor layer 33 and the lower capacitor electrode 46 are both formed of polycrystalline silicon, and the lower capacitor electrode 46 has been subjected to doping by an ion implantation method or otherwise. Therefore, the resistance of the lower capacitor electrode 46 is small. A gate insulation film 49 overlies both the semiconductor layer 33 and the lower capacitor electrode 46.
As shown in FIG. 4, a gate bus line 40 and an additional capacitor common line 44 is laid in parallel relation to the semiconductor layer 33. As can be seen from FIG. 6, the gate bus line 40, as well as the semiconductor layer 33, is formed on the substrate 30, while the additional capacitor common line 44 is formed on the gate insulation film 49. A part of the additional capacitor common line 44 functions as an upper capacitor electrode of the additional capacitor 32. The gate bus line 40 and additional capacitor common line 44 are formed of n.sup.+ or p.sup.+ polycrystalline silicon from the standpoint of thermal stability in a subsequent heat treating stage. Gate electrodes 42a and 42b are branched from the gate bus line 40 toward two TFTs 31a and 31b respectively. In this example, two TFTs are arranged in series. With the foregoing arrangement it is possible to reduce current leakage from the TFTs.
An interlayer insulation film 47 is formed on and above the substrate 30. On opposite end portions of the semiconductor layer 33 there are formed contact holes 43a and 43b which extend through both the interlayer insulation film 47 and the gate insulation film 49. As shown in FIG. 4, contact holes 43a are provided in such a way that each source bus line 41 extending across gate bus lines 40 runs over the top of the relevant contact holes 43a. Each source bus line 41 is formed larger in width at each portion thereof which is located above a contact hole 43a. A pixel electrode 45 extends on each contact hole 43b. Each source bus line 41 is formed of a low-resistance metal, such as Al, and each pixel electrode 45 is formed of ITO (Indium Tin Oxide). In this way, the source bus line 41 and the semiconductor layer 33 are electrically connected at the contact hole 43a. Similarly, the pixel electrode 45 and the semiconductor layer 33 are electrically connected at the contact hole 43b. A protective film 48 is formed covering the substrate 30. Further, a gate drive circuit and a source drive circuit (both not shown) which are similar to those shown in FIG. 7 are formed on this active matrix substrate.
The display device using this active matrix substrate is driven in the following way. Initially, a gate-ON signal is output from the gate drive circuit sequentially to individual gate bus lines 40. Thereupon, TFTs 31a and 31b connected to the gate bus lines 40 to which the ON signal is applied are turned on simultaneously. In the source drive circuit (not shown) there are provided TFTs in corresponding relation to individual source bus lines 41, each of these TFTs performs switching between each source bus line 41 and an associated video signal line. Such a TFT, known as "an analog switch", has a function to electrically interconnect the source bus line 41 and the associated video line only when a video signal for corresponding picture elements is being sent. After the video signal is written in the source bus line 41 through the analog switch, the analog switch is turned off, and in turn a further video signal is written in another source bus line 41, and so on.
Each written video signal is retained through the utilization of a parasitic capacity of the source bus line 41. This system is known as "a panel sample hold system". If necessary, there may be provided a capacity for supplementing this parasitic capacity. The panel sample hold system has an advantage that it affords reduction of the area of the drive circuits. Each video signal held by the source bus line 41 is written in an associated pixel electrode 45 and additional capacitor electrode 46 through the TFTs 31a and 31b. In this case, a current for supplying a charge corresponding to the video signal flows in the additional capacitor common line 44 opposite to the additional capacitor electrode 46 in which the video signal is written. After video signals are written in all of the source bus lines 41 intersecting one on-condition gate bus line 40, the gate bus line 40 is turned off.
In such an active matrix substrate, there is a reasonably long time after one of the gate bus lines 40 is turned on and before the one gate bus line 40 is turned off and, therefore, in an initially turned-on source bus line 41, enough time is available to write video signals in the pixel electrodes 45 and additional capacitor electrodes 46. However, in a source bus line 41 which is finally turned on, time available before the gate bus line 40 is turned off is so short that the time for writing video signals is considerably limited. Moreover, in the active matrix substrate shown in FIG. 4, the additional capacitor common lines 44 are formed of n.sup.+ or p.sup.+ polycrystalline silicon and, therefore, the resistance thereof cannot be said to be reasonably small. This gives rise to a problem that there may occur a signal delay on the additional capacitor common line 44, with the result that video signals cannot be written within the limited time, which in turn may cause fluctuations in the potential of signals written in the pixel electrodes 45.
To explain this problem, an equivalent circuit diagram representing one pixel portion is shown in FIG. 8. A capacity C.sub.LC enclosing a liquid crystal layer is positioned between a pixel electrode connected to a drain electrode of a TFT and a counter electrode line connected to a counter electrode. The drain electrode of the TFT is connected to an additional capacitor common line through an additional capacitor C.sub.s. A capacity C.sub.gd is formed between a gate electrode of the TFT and the drain electrode. When a gate-ON signal is sent to a gate bus line of the TFT, the TFT is turned on and a video signal voltage V.sub.d is written in a source bus line. Where the time constant for signal transmission on the additional capacitor common line is .tau..sub.cs, and time for writing a signal in the pixel electrode is T.sub.ON, charging of the additional capacitor is insufficient if condition .tau..sub.cs &lt;&lt;T.sub.ON is not satisfied, with the result that the potential of the pixel electrode fluctuates. Potential Vd' of the pixel electrode which corresponds to actual display condition in which the TFT has been turned off and a reasonably longer time than .tau..sub.cs has passed thereafter may be expressed by the following equation (1) ##EQU1## where V.sub.g represents the difference between the gate potential at the time when TFT is ON and the gate potential at the time when TFT is OFF: and a is expressed by the following relation and represents potential variation caused due to the fact that the additional capacitor cannot sufficiently be charged during the write time. ##EQU2## In equation (1), the second term represents the variation of the voltage at the pixel electrode due to the voltage fluctuation on the gate bus line which results from the TFT being turned off. In order to attain good fidelity of display according to the written video signal, the values of the second term in equation (1) and of a in equation (2) must be made smaller. In order to decrease the value of the second term in equation (1), it is necessary that the following relation holds: EQU C.sub.gd &lt;&lt;C.sub.LC +C.sub.2 ( 3)
In a high-precision active matrix substrate, pixel electrodes are very small and therefore C.sub.LC is small. Therefore, in order to satisfy the conditions of equation (3), an additional capacitor C.sub.s of a certain level or above is required. Since such a higher level of additional capacitor C.sub.s is required, in order to decrease the value of the third term in equation (1), that is, the value of a in equation (2), it is necessary that the following relation should hold: EQU T.sub.ON &gt;&gt;.tau..sub.cs ( 4)
Especially in a small size, high-precision active matrix substrate wherein drive circuits and TFT array are formed on a common substrate, it is difficult to satisfy the conditions of equation (4). The reasons may be as follows;
(1) A larger number of gate bus lines is involved, so that time allocatable to each gate bus line is shorter.
(2) Whereas, in the driver IC mounting system, video signals are output simultaneously to all source bus lines, the panel sample hold system is such that video signals are output sequentially to individual source bus lines, with the result that the time allowed for writing in a source bus line in which writing is lastly made is much shorter.
(3) In order to avoid a possible decrease in aperture ratio due to the adoption of high-precision display system, it is necessary to reduce the width of individual lines, this results in increased resistance of the additional capacitor common lines, it being thus impracticable to reduce the value of .tau..sub.cs.
(4) While the number of picture elements is increased, the size of additional capacitor electrode for each picture element cannot be reduced. As a result, the sum of additional capacities connected to one additional capacitor common line becomes grater, it being thus impracticable to reduce the value of .tau..sub.cs.
As a solution to these problems, it may be conceivable, for example, to connect each additional capacitor common line at both end portions thereof to an electrode of the same potential as a counter electrode. But this cannot be said to be a good solution. A redundant structure is often employed with additional capacitor common lines, but a problem here is that such a redundant structure cannot be well utilized unless the value of .tau..sub.cs is reasonably smaller than T.sub.ON.